Verification Engineer Resume Sample

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Albert Wesley

Verification Engineer

Proving silicon works before it ever ships

[email protected]
+91 80 5550 0720
linkedin.com/in/albert-wesley-dv

Verification engineer with nine years verifying digital designs for a semiconductor company in Bangalore. Builds the testbenches and environments that prove a chip design works correctly before it is committed to silicon, where a missed bug is extremely costly. Built a reusable verification environment that improved coverage and caught corner-case bugs earlier. Develops verification plans and SystemVerilog/UVM testbenches, writes assertions and coverage, debugs failures with designers, and drives functional verification to closure. Strong on both the deep technical verification skill and the rigour the role demands, where correctness is everything. Methodical, thorough and relentless about coverage. Looking for a verification, design-verification or DV-engineer role with a semiconductor or hardware company building serious silicon.

LocationBangalore, India
NationalityIndian
GenderMale
Notice Period2 months
Date of Birth1990-09-19
Work Experience
(April 2014 to Present)12 years & 4 months

Bangalore Semiconductors - Bangalore, India

Verification Engineer

Build all the testbenches and the environments that prove the digital designs work before silicon.
Built a reusable verification environment that improved the coverage and caught corner-case bugs earlier.
Develop all the verification plans and the SystemVerilog and UVM testbenches for blocks and chips.
Write all the assertions and the functional coverage and debug all the failures with the designers.
Drive all the functional verification right through to closure with the thorough coverage analysis throughout.
Apply real rigour, knowing a single missed bug in the silicon is extremely costly to fix.
(August 2011 to March 2014)2 years & 8 months

South India Chip Design - Bangalore, India

Junior Verification Engineer

Built the testbench components and ran the verification under the senior engineers.
Debugged all the failures and worked on the full coverage closure there.
Learned the SystemVerilog, the UVM and the verification methodology on real chips.
Gained the verification certification and then moved into a verification-engineer role.
(June 2009 to July 2011)2 years & 2 months

South India Chip Design - Bangalore, India

RTL Design Engineer

Worked as an RTL engineer designing and coding the digital logic blocks.
Learned the Verilog, the design flow and how chips come together.
Built up the design grounding that good verification is built on.
Then earned the move into a full junior verification-engineer role from there.
Education
(July 2007 to May 2011)3 years & 11 months

RV College of Engineering, Bangalore

BE in Electronics & Communication Engineering - Electronics Engineering

Electronics and communication engineering degree covering digital design, VLSI and verification. The VLSI focus led directly into design verification. Built the technical foundation the role requires.
(January 2014 to June 2014)6 months

Industry Training Provider

SystemVerilog & UVM Verification Certification - Design Verification

Certification in SystemVerilog and UVM verification covering testbenches, coverage and methodology. It formalised the verification toolkit used daily. Applied directly to testbench development and verification.
Technical Skills
  • Functional Verification
  • SystemVerilog
  • UVM
  • Testbench Development
  • Assertions (SVA)
  • Functional Coverage
  • Verification Planning
  • Debugging
  • Digital Design
  • Coverage Closure
Languages

English

Full Professional Proficiency

Hindi

Native or Bilingual Proficiency

Kannada

Professional Working Proficiency
Highlights

Caught corner-case bugs

Built a reusable verification environment that improved coverage and caught corner-case bugs earlier. Finding bugs before tape-out saves enormous cost and respins.

Relentless on coverage

Drives functional verification to thorough closure, knowing a missed bug in silicon is hugely costly. In verification, relentless rigour is the whole job.
Reusable Verification Environment

UVM Methodology Framework

Verification Engineer (January 2018 to December 2018)

Built a reusable UVM framework of components and sequences the whole team adopted, so new blocks were verified faster and to a consistent, high standard across every project.

Coverage Closure Drive

Verification Engineer (January 2020 to October 2020)

Led the coverage-closure drive on a complex chip, building the missing tests and assertions to hit the targets so the design taped out with confidence and no expensive late respins.
Certifications

SystemVerilog & UVM Verification

Industry Training Provider (June 2014 to Present)

Certification in SystemVerilog and UVM verification covering testbenches, coverage and methodology. It formalised the verification toolkit used daily. Applied directly to testbench development and verification.

Formal Verification & Coverage

Accellera (April 2019 to Present)

Certification in formal verification and coverage covering assertions, properties and closure. It supports the rigorous coverage analysis and the bug-finding done across the verification work.
Personal Skills
  • Attention to Detail
  • Analytical Thinking
  • Thoroughness
  • Persistence
  • Methodical Approach
Activities & Interests
Gymnastic
Badminton
Historic places
Boating
Web Surfing

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